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emmc ? memory n2m400fdb311a3c[e/f], n2m400gdb321a3c[e/f] n2m400hdb321a3c[e/f], N2M400JDB341A3C[e/f] features ? multimediacard (mmc) controller and nand flash ? 100-ball lbga (rohs 6/6- compliant) ? v cc : 2.7C3.6v ? v ccq (dual voltage): 1.65C1.95v; 2.7C3.6v ? temperature ranges C industrial temperature: C40?c to +85?c C storage temperature: C40?c to +85?c ? typical current consumption C standby current: 70 a (4gb, 8gb); 90a (16gb, 32gb) C active current (rms): 70ma (4gb, 8gb); 90ma (16gb, 32gb) mmc-specific features ? jedec/mmc standard version 4.41-compliant (jedec standard no. 84-a441) C spi mode not supported (see www.jedec.org/sites/default/files/ docs/jesd84-a441.pdf ) C advanced 11-signal interface C x1, x4, and x8 i/os, selectable by host C mmc mode operation C command classes: class 0 (basic); class 2 (block read); class 4 (block write); class 5 (erase); class 6 (write protection); class 7 (lock card) C mmc plus ? and mmc mobile ? protocols C temporary write protection C 52 mhz clock speed (max) C boot operation (high-speed boot) C sleep mode C replay-protected memory block (rpmb) C secure erase and trim C hardware reset signal C multiple partitions with enhanced attribute C permanent and power-on write protection C double data rate (ddr) function C high-priority interrupt (hpi) figure 1: micron e mmc device mmc controller mmc power nand flash power mmc interface nand flash mmc-specific features (continued) C enhanced reliable write C configurable reliability settings C background operation C fully enhanced configurable C backward-compatible with previous mmc modes ? ecc and block management implemented micron confidential and proprietary preliminary ? 4gb, 8gb, 16gb, 32gb: emmc features pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. ?products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet microns production data sheet specifications.
e mmc performance table 1: mlc partition performance condition part number units n2m400fdb311a3c[e/f] n2m400gdb321a3c[e/f] n2m400hdb321a3c[e/f] N2M400JDB341A3C[e/f] sequential write 13.5 20 mb/s sequential read 44 44 mb/s note: 1. sequential access of 1mb chunk. additional performance data, such as power consumption or timing for dif- ferent device modes, will be provided in a separate document upon customer request. ordering information table 2: ordering information base part number density package nand flash type shipping media n2m400fdb311a3c[e/f] 4gb 100-ball lbga 14.0mm x 18.0mm x 1.4mm 1 x 32gb, mlc, 25nm tray tape and reel n2m400gdb321a3c[e/f] 8gb 100-ball lbga 14.0mm x 18.0mm x 1.4mm 2 x 32gb, mlc, 25nm tray tape and reel n2m400hdb321a3c[e/f] 16gb 100-ball lbga 14.0mm x 18.0mm x 1.4mm 2 x 64gb, mlc, 25nm tray tape and reel N2M400JDB341A3C[e/f] 32gb 100-ball lbga 14.0mm x 18.0mm x 1.4mm 4 x 64gb, mlc, 25nm tray tape and reel micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc features pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
part numbering information micron ? e mmc memory devices are available in different configurations and densities. verify valid part numbers by using microns part catalog search at www.micron.com . to compare features and specifications by device type, visit www.micron.com/products . contact the factory for devices not found. figure 2: marketing part number chart n2m 4 00f d b 3 1 1a3 c e managed nand emmc version 4 = version 4.41 density 00f = 4gb 00g = 8gb 00h = 16gb 00j = 32gb lytho d = 25nm temperature range b = extended (C40c to +85c) media e = tray f = tape and reel firmware id c = combo package 1a3 = 100-ball lbga (14 x 18 x 1.4mm - 1mm) configuration 1 = 1 die 2 = 2 die 4 = 4 die voltage 3 = 3.0v note: 1. not all combinations are necessarily available. for a list of available devices or for further information on any aspect of these products, please contact your nearest micron sales office. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc features pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
general description micron e mmc is a communication and mass data storage device that includes a multi- mediacard (mmc) interface, a nand flash component, and a controller on an ad- vanced 11-signal bus, which is compliant with the mmc system specification. its cost per bit, small package sizes, and high reliability make it an ideal choice for industrial applications like infrastructure and networking equipment, pc and servers, a variety of other industrial products. the nonvolatile e mmc draws no power to maintain stored data, delivers high perform- ance across a wide range of operating temperatures, and resists shock and vibration dis- ruption. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc general description pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
signal descriptions table 3: signal descriptions symbol type description clk input clock: each cycle of the clock directs a transfer on the command line and on the data line(s). the frequency can vary between the minimum and the maximum clock frequency. rst_n input reset: the rst_n signal is used by the host for resetting the device, moving the device to the pre- idle state. by default, the rst_n signal is temporarily disabled in the device. the host must set ecsd register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it. cmd i/o command: this signal is a bidirectional command channel used for command and response trans- fers. the cmd signal has two bus modes: open-drain mode and push-pull mode (see operating modes). commands are sent from the mmc host to the device, and responses are sent from the device to the host. dat[7:0] i/o data i/o: these are bidirectional data signals. the dat signals operate in push-pull mode. by de- fault, after power-on or assertion of the rst_n signal, only dat0 is used for data transfer. the mmc controller can configure a wider data bus for data transfer either using dat[3:0] (4-bit mode) or dat[7:0] (8-bit mode). e mmc includes internal pull-up resistors for data lines dat[7:1]. immedi- ately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the dat[3:1] lines. upon entering the 8-bit mode, the device disconnects the internal pull-ups on the dat[7:1] lines. v cc supply v cc : nand interface (i/f) i/o and nand flash power supply. v ccq supply v ccq : e mmc controller core and e mmc i/f i/o power supply. v ss 1 supply v ss : nand i/f i/o and nand flash ground connection. v ssq 1 supply v ssq : e mmc controller core and e mmc i/f ground connection. v ddi internal voltage node: at least a 0.1 f capacitor is required to connect v ddi to ground. a 1 f ca- pacitor is recommended. do not tie to supply voltage or ground. nc C no connect: no internal connection is present. rfu C reserved for future use: no internal connection is present. leave it floating externally. note: 1. v ss and v ssq are connected internally. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc signal descriptions pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
100-ball signal assignments figure 3: 100-ball lfbga (top view, ball down) 1 2 3 4 5 6 7 8 9 10 a b d e f g h j k l m n p t u a b d e f g h j k l m n p t u nc nc nc nc nc rfu rfu v cc v ss v ssq rfu d a t0 v ccq rfu d a t1 v ssq nc rfu rfu v cc v ss v ccq rfu d a t2 v ssq rfu d a t3 v ccq rfu v ddi v cc v ss rfu rfu rfu v ccq v ssq rfu rfu rfu rfu v cc v ss rfu rfu rfu rfu rst_n rfu cmd rfu rfu v cc v ss rfu rfu rfu rfu rfu rfu clk rfu rfu v cc v ss rfu rfu rfu v ccq v ssq rfu rfu rfu rfu v cc v ss v ccq rfu d a t5 v ssq rfu d a t4 v ccq nc rfu rfu v cc v ss v ssq rfu d a t7 v ccq rfu d a t6 v ssq nc nc nc nc nc note: 1. connect a 1 f decoupling capacitor from v ddi to ground. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc 100-ball signal assignments pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
package dimensions figure 4: 100-ball lbga C 14.0mm x 18.00mm x 1.4mm (package code 1a3) ball a1 id ball a1 id 0.12 a a 1.01 0.1 100x ?0.45 solder ball material: sac305. dimensions apply to solder balls post- reflow on ?0.4 smd ball pads. 16 ctr 18 0.1 1 typ 9 ctr 14 0.1 1.4 max 0.25 min seating plane 1 typ 10 9 8 7 6 5 4 3 2 1 a b d e f g h j k l m n p t u test pads. ni/au plated. no solder balls. note: 1. dimensions are in millimeters. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc package dimensions pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
architecture figure 5: e mmc functional block diagram rst_n cmd clk v ddi v cc v ccq d a t[7:0] v ss 1 v ssq 1 mmc controller emmc nand flash registers ocr csd rca cid ecsd dsr note: 1. v ss and v ssq are internally connected. mmc protocol independent of nand flash technology the mmc specification defines the communication protocol between a host and a de- vice. the protocol is independent of the nand flash features included in the device. the device has an intelligent on-board controller that manages the mmc communica- tion protocol. the controller also handles block management functions such as logical block alloca- tion and wear leveling. these management functions require complex algorithms and depend entirely on nand flash technology (generation or memory cell type). the device handles these management functions internally, making them invisible to the host processor. defect and error management micron e mmc incorporates advanced technology for defect and error management. if a defective block is identified, the device completely replaces the defective block with one of the spare blocks. this process is invisible to the host and does not affect data space allocated for the user. the device also includes a built-in error correction code (ecc) algorithm to ensure that data integrity is maintained. to make the best use of these advanced technologies and ensure proper data loading and storage over the life of the device, the host must exercise the following precautions: ? check the status after write, read, and erase operations. ? avoid power-down during write and erase operations. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc architecture pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
cid register the card identification (cid) register is 128 bits wide. it contains the device identifica- tion information used during the card identification phase as required by e mmc proto- col. each device is created with a unique identification number. table 4: cid register field parameters name field width cid bits cid value manufacturer id mid 8 [127:120] feh reserved C 6 [119:114] C card/bga cbx 2 [113:112] 01h oem/application id oid 8 [111:104] C product name pnm 48 [103:56] mmc04g mmc08g mmc16g mmc32g product revision prv 8 [55:48] C product serial number psn 32 [47:16] C manufacturing date mdt 8 [15:8] C crc7 checksum crc 7 [7:1] C not used; always 1 C 1 0 C micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc cid register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
csd register the card-specific data (csd) register provides information about accessing the device contents. the csd register defines the data format, error correction type, maximum da- ta access time, and data transfer speed, as well as whether the ds register can be used. the programmable part of the register (entries marked with w or e in the following ta- ble) can be changed by the program_csd (cmd27) command. table 5: csd register field parameters name field width cell type 1 csd bits csd value csd structure csd_structure 2 r [127:126] 03h system specification version spec_vers 4 r [125:122] 4h reserved 2 C 2 tbd [121:120] C data read access time 1 taac 8 r [119:112] 4fh data read access time 2 in clk cy- cles (nsac 100) nsac 8 r [111:104] 01h maximum bus clock frequency tran_speed 8 r [103:96] 32h card command classes ccc 12 r [95:84] 0f5h maximum read data block length read_bl_len 4 r [83:80] 9h partial blocks for reads supported read_bl_partial 1 r 79 0h write block misalignment write_blk_misalign 1 r 78 0h read block misalignment read_blk_misalign 77 r 77 0h ds register implemented dsr_imp 1 r 76 1h reserved C 2 r [75:74] C device size c_size 12 r [73:62] fffh maximum read current at v dd,min vdd_r_curr_min 3 r [61:59] 7h maximum read current at v dd,max vdd_r_curr_max 3 r [58:56] 7h maximum write current at v dd,min vdd_w_curr_min 3 r [55:53] 7h maximum write current at v dd,max vdd_w_curr_max 3 r [52:50] 7h device size multiplier c_size_mult 3 r [49:47] 7h erase group size erase_grp_size 5 r [46:42] 1fh erase group size multiplier erase_grp_mult 5 r [41:37] 1fh write protect group size wp_grp_size n2m400fdb311a3c[e/f] 5 r [36:32] 07h n2m400gdb321a3c[e/f] 0fh n2m400hdb321a3c[e/f] N2M400JDB341A3C[e/f] 1fh write protect group enable wp_grp_enable 1 r 31 1h manufacturer default ecc default_ecc 2 r [30:29] 0h rite-speed factor r2w_factor 3 r [28:26] 2h micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc csd register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 5: csd register field parameters (continued) name field width cell type 1 csd bits csd value maximum write data block length write_bl_len 4 r [25:22] 9h partial blocks for writes suppor- ted write_bl_partial 1 r 21 0h reserved C 4 r [20:17] C content protection application content_prot_app 1 r 16 0h file-format group file_format_grp 1 r/w 15 0h copy flag (otp) copy 1 r/w 14 0h permanent write protection perm_write_protect 1 r/w 13 0h temporary write protection tmp_write_protect 1 r/w/e 12 0h file format file_format 2 r/w [11:10] 0h ecc ecc 2 r/w/e [9:8] 0h crc crc 7 r/w/e [7:1] C not used; always 1 C 1 C 0 1h notes: 1. r = read-only r/w = one-time programmable and readable r/w/e = multiple writable with value kept after a power cycle, assertion of the rst_n signal, and any cmd0 reset, and readable tbd = to be determined 2. reserved bits should be read as 0. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc csd register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
ecsd register the 512-byte extended card-specific data (ecsd) register defines device properties and selected modes. the most significant 320 bytes are the properties segment. this seg- ment defines device capabilities and cannot be modified by the host. the lower 192 bytes are the modes segment. the modes segment defines the configuration in which the device is working. the host can change the properties of modes segments using the switch command. table 6: ecsd register field parameters name field size (bytes ) cell type 1 ecsd bytes ecsd value properties segment reserved 2 C 7 C [511:505] C supported command sets s_cmd_set 1 r 504 1h hpi features hpi_features 1 r 503 3h background operations sup- port bkops_support 1 r 502 1h reserved C 255 C [501:247] C background operations status bkops_status 1 r 246 0h number of correctly program- med sectors correctly_prg_ sectors_num 4 r [245:242] C first initialization time after partitioning (first cmd1 to device ready) ini_timeout_pa n2m400fdb311a3c[e/f] 1 r 241 78h n2m400hdb321a3c[e/f] f4h n2m400gdb321a3c[e/f] f6h N2M400JDB341A3C[e/f] ffh reserved C 1 C 240 C power class for 52 mhz, ddr at 3.6v 3 pwr_cl_ddr_52_360 1 r 239 0h power class for 52 mhz, ddr at 1.95v 3 pwr_cl_ddr_52_195 1 r 238 0h reserved C 2 C [237:236] C minimum write performance for 8-bit at 52 mhz in ddr mode min_perf_ddr_w_8_52 1 r 235 0h minimum read performance for 8-bit at 52 mhz in ddr mode min_perf_ddr_r_8_52 1 r 234 0h reserved C 1 C 233 C trim multiplier trim_mult n2m400fdb311a3c[e/f], n2m400gdb321a3c[e/f] 1 r 232 06h n2m400hdb321a3c[e/f], N2M400JDB341A3C[e/f] 0fh secure feature support sec_feature_support 1 r 231 15h micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc ecsd register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 6: ecsd register field parameters (continued) name field size (bytes ) cell type 1 ecsd bytes ecsd value secure erase multiplier sec_erase_mul t n2m400fdb311a3c[e/f], n2m400gdb321a3c[e/f] 1 r 230 02h n2m400hdb321a3c[e/f], N2M400JDB341A3C[e/f] 06h secure trim multiplier sec_trim_mult n2m400fdb311a3c[e/f], n2m400gdb321a3c[e/f] 1 r 229 03h n2m400hdb321a3c[e/f], N2M400JDB341A3C[e/f] 09h boot information boot_info 1 r 228 7h reserved C 1 C 227 C boot partition size boot_size_mul t 1 r 226 80h access size acc_size n2m400fdb311a3c[e/f], n2m400gdb321a3c[e/f] 1 r 225 06h n2m400hdb321a3c[e/f], N2M400JDB341A3C[e/f] 07h high-capacity erase unit size hc_erase_grp_s ize n2m400fdb311a3c[e/f], n2m400gdb321a3c[e/f] 1 r 224 08h n2m400hdb321a3c[e/f], N2M400JDB341A3C[e/f] 10h high-capacity erase timeout erase_timeout_mult 1 r 223 01h reliable write-sector count rel_wr_sec_c 1 r 222 01h high-capacity write protect group size hc_wp_grp_size n2m400fdb311a3c[e/f] 1 r 221 01h n2m400gdb321a3c[e/f], n2m400hdb321a3c[e/f] 02h N2M400JDB341A3C[e/f] 04h sleep current (v cc ) s_c_vcc 1 r 220 08h sleep current (v ccq ) s_c_vccq 1 r 219 08h reserved C 1 C 218 C sleep/awake timeout s_a_timeout 1 r 217 10h reserved C 1 C 216 C sector count sec_count n2m400fdb311a3c[e/f] 4 r [215:212] 0070c000h n2m400hdb321a3c[e/f] 00e88000h n2m400gdb321a3c[e/f] 01d30000h N2M400JDB341A3C[e/f] 03b20000h reserved C 1 C 211 C minimum write performance for 8-bit at 52 mhz min_perf_w_8_52 1 r 210 08h micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc ecsd register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 6: ecsd register field parameters (continued) name field size (bytes ) cell type 1 ecsd bytes ecsd value minimum read performance for 8-bit at 52 mhz min_perf_r_8_52 1 r 209 08h minimum write performance for 8-bit at 26 mhz and 4-bit at 52 mhz min_perf_w_8_26_4_52 1 r 208 08h minimum read performance for 8-bit at 26 mhz and 4-bit at 52 mhz min_perf_r_8_26_4_52 1 r 207 08h minimum write performance for 4-bit at 26 mhz min_perf_w_4_26 1 r 206 08h minimum read performance for 4-bit at 26 mhz min_perf_r_4_26 1 r 205 08h reserved C 1 C 204 C power class for 26 mhz at 3.6v 3 pwr_cl_26_360 1 r 203 00h power class for 52 mhz at 3.6v 3 pwr_cl_52_360 1 r 202 00h power class for 26 mhz at 1.95v 3 pwr_cl_26_195 1 r 201 00h power class for 52 mhz at 1.95v 3 pwr_cl_52_195 1 r 200 00h partition switching timing partition_switch_time 1 r 199 1h out-of-interrupt busy timing out_of_interrupt_time 1 r 198 02h reserved C 1 C 197 C card type card_type 1 r 196 07h reserved C 1 C 195 C csd structure version csd_structure 1 r 194 2h reserved C 1 C 193 C extended csd revision ext_csd_rev 1 r 192 5h modes segment command set cmd_set 1 r/w/e_ p 191 0h reserved C 1 C 190 C command set revision cmd_set_rev 1 r 189 0h reserved C 1 C 188 C power class power_class 1 r/w/e_ p 187 0h reserved C 1 C 186 C micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc ecsd register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 6: ecsd register field parameters (continued) name field size (bytes ) cell type 1 ecsd bytes ecsd value high-speed interface timing hs_timing 1 r/w/e_ p 185 0h reserved C 1 C 184 C bus width mode bus_width 1 w/e_p 183 0h reserved C 1 C 182 C erased memory content erased_mem_cont 1 r 181 0h reserved C 1 C 180 C partition configuration partition_config 1 r/w/e, r/w/e_ p 179 0h boot configuration protection boot_config_prot 1 r/w, r/w/c_ p 178 0h boot bus width boot_bus_width 1 r/w/e 177 0h reserved C 1 C 176 C high-density erase group defi- nition erase_group_def 1 r/w/e_ p 175 00h reserved C 1 C 174 C boot area write protection reg- ister boot_wp 1 r/w, r/w/c_ p 173 0h reserved C 1 C 172 C user write protection register user_wp 1 r/w, r/w/ c_p, r/w/e_ p 171 0h reserved C 1 C 170 C firmware configuration fw_config 1 r/w 169 0h rpmb size rpmb_size_mult 1 r 168 1h write reliability setting regis- ter 3 wr_rel_set 1 r/w 167 00h 4 write reliability parameter reg- ister wr_rel_param 1 r 166 05h reserved C 1 C 165 C manually start background op- erations bkops_start 1 w/e_p 164 C enable background operations handshake bkops_en 1 r/w 163 0h hardware reset function rst_n_function 1 r/w 162 0h micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc ecsd register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 6: ecsd register field parameters (continued) name field size (bytes ) cell type 1 ecsd bytes ecsd value hpi management hpi_mgmt 1 r/w/e_ p 161 0h partitioning support partitioning_support 1 r 160 3h maximum enhanced area size max_enh_size_ mult n2m400fdb311a3c[e/f] 3 r [159:157] 0001c3h n2m400hdb321a3c[e/f] 0001d1h n2m400gdb321a3c[e/f] 0001d3h N2M400JDB341A3C[e/f] 0001d9h partitions attribute partitions_attribute 1 r/w 156 0h partitioning setting partition_setting_completed 1 r/w 155 0h general-purpose partition size gp_size_mult 12 r/w [154:143] 0h enhanced user data area size enh_size_mult 3 r/w [142:140] 0h enhanced user data start ad- dress enh_start_addr 4 r/w [139:136] 0h reserved C 1 C 135 C bad block management mode sec_bad_blk_mgmnt 1 r/w 134 0h reserved C 134 C [133:0] C notes: 1. r = read-only r/w = one-time programmable and readable r/w/e = multiple writable with the value kept after a power cycle, assertion of the rst_n signal, and any cmd0 reset, and readable r/w/c_p = writable after the value is cleared by a power cycle and assertion of the rst_n signal (the value not cleared by cmd0 reset) and readable r/w/e_p = multiple writable with the value reset after a power cycle, assertion of the rst_n signal, and any cmd0 reset, and readable w/e_p = multiple writable with the value reset after power cycle, assertion of the rst_n signal, and any cmd0 reset, and not readable tbd = to be determined 2. reserved bits should be read as 0. 3. micron has tested power failure under best application knowledge conditions with posi- tive results. customers may request a dedicated test for their specific application condi- tion. 4. set at 00h when shipped for optimized write performance; can be set to 1fh to enable protection on previously written data if power failure occurs during a write operation. this byte is one-time programmable. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc ecsd register pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
dc electrical specifications C device power the device current consumption for various device configurations is defined in the power class fields of the ecsd register. v cc is used for the nand flash device and its interface voltage; v ccq is used for the controller and the e mmc interface voltage. a c reg capacitor must be connected to the v ddi terminal to stabilize regulator output on the system. figure 6: device power diagram nand control signals nand flash mmc controller core regulator nand i/o block mmc i/o block core logic block clk cmd dat[7:0] v cc v ddi c reg v ccq nand data bus note: stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 7: absolute maximum ratings parameters symbol min max unit voltage input v in C0.6 4.6 v v cc supply v cc C0.6 4.6 v v ccq supply v ccq C0.6 4.6 v storage temperature t stg C40 85 c note: 1. voltage on any pin relative to v ss . micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc dc electrical specifications C device power pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 8: operating conditions parameters symbol min typ max unit supply voltage (controller and i/o) v ccq 1.65 C 1.95 v 2.70 C 3.6 supply voltage (nand) v cc 2.70 C 3.6 v supply power-on for 3.3v t pruh C C 35 ms supply power-on for 1.8v t prul C C 25 ms v ddi capacitance value c reg 1 0.1 C C f operating temperature t a C40 C 85 oc note: 1. c reg is used to stabilize the internal regulator output to controller core logic voltages. micron recommends using the following capacitor values: c vcc (capacitor for v cc ) = 4.3f. c vccq (capacitor for v ccq ) = 4.3f c reg = 1.0f. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc dc electrical specifications C device power pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
revision history rev. c C 7/12 ? updated mmc-specific features ? updated ordering information table ? updated 160-ball lbga package dimension drawing (package code 1a3) ? added part numbering information ? corrected typos in cid and ecsd register tables ? added note 4 to ecsd register table ? updated csd[36:32] and ecsd[bytes 241, 222, 215:212, 175, 167, 166, 159:157] regis- ter tables rev. b C 2/12 ? changed the part numbers and the minimum operating temperature from -25 to -40 degrees c rev. a C 1/12 ? initial release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. micron confidential and proprietary preliminary 4gb, 8gb, 16gb, 32gb: emmc revision history pdf: 09005aef84a4d6f1 emmc_4gb_8gb_16gb_32gb_100b-it.pdf - rev. c 7/12 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.

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